a. Field of the Invention
The present invention pertains to integrated circuit manufacturing and specifically to test samples used to qualify a new manufacturing process.
b. Description of the Background
In the development of a new manufacturing process for integrated circuits (interconnect modules), certain design rules are created that define the capabilities of the process. A designer begins the design of new integrated circuits at the same time as the manufacturing capability is being developed. The concurrency of new process development and product design places great importance on the ability of the manufacturing process to be able to produce integrated circuits using those design rules.
The design rules include such things as minimum trace width, minimum distance between traces, the maximum number of vias that may be stacked on top of each other, and other such parameters. Typically, a manufacturer may guarantee that a process will manufacture good parts if the parts conform to the design rules, thus allowing the designers to begin integrated circuit designs many months before the manufacturing process is ready.
After the first production of a new integrated circuit design, there is generally a period of failure analysis as the design and manufacturing processes are adjusted to produce a successful product. The root cause failure analysis of some integrated circuits may be very time consuming, sometimes consuming days or even weeks to isolate a single fault on a chip.
The failure analysis techniques available to development engineers include mechanical probing, optical beam induced current (OBIC), optical beam induced resistive change (OBIRCH), picosecond imaging circuit analysis (PICA), light induced voltage alterations (LIVA), charge induced voltage alterations (CIVA), various scanning electron microscopy (SEM) techniques, and other techniques known in the art. In addition, destructive tests, such as etching and lapping, may be used to isolate and identify problems.
In many cases, the design of an integrated circuit may limit or prohibit certain techniques for ascertaining faults. For example, in order to probe a certain path using a laser technique, the path must not have another metal trace directly above the path of interest. Further, the various techniques may only isolate a problem within a certain section of the circuitry, but not to a specific trace or via.
During process development and verification, it is important that faults are isolated to an exact location. For example, a via may have very high resistivity. In order for the manufacturing process to be corrected, the location of the via must be identified exactly. Failure analysis techniques that isolate only a section of an electric path are not sufficient for the fine-tuning of the manufacturing process.
Memories can be self-timed circuits and the location of the fault in the memory array can be shown based on test program data logs. This is typically referred to as bit mapping. The bit mapping routines typically consume thousands of megabytes of tester memory and require many test pins to test. Memories typically only look at the first few layers or a process and do not have typical structures seen in analog circuits or in digital circuits.
Memories require expensive test platforms for testing due to the high tester pattern memory requirements and cannot look at all process layers or subsets of layers for yield and reliability. Memory structures are fixed and do not look like analog circuits or digital circuits and therefore suffer from the same yield or reliability issues. Commercially available fault tester systems such as PDF Solutions and KLA Microloop structures that use SEM or Optical inspection are very slow to test, cannot be used for reliability testing and increase the cycle time though manufacturing.
Failure analysis, particularly on 90 nm technologies and beyond is becoming extremely difficult. At-speed testing, which is the process of placing an application specific integrated circuit (ASIC) or interconnect module on a tester and running fault coverage and performance test patterns at the speed the part will run in the system, is becoming very important to the yield and reliability of products.
It would therefore be advantageous to provide a system and method for testing an integrated circuit manufacturing process wherein failure analysis techniques may be used to quickly isolate and locate a manufacturing defect and be fast enough to be utilized for reliability testing. It would further be advantageous if the system and method were able to stress the manufacturing process by operating at the design limits of the manufacturing process.